Exemplary embodiments of the present invention relate to a semiconductor device designing technology, and more particularly, to a semiconductor memory device and a semiconductor memory system including the same.
The operation speed and the integration degree of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device continue to increase. In increasing the operation speed of the DRAM device, a Synchronous Dynamic Random Access Memory (SDRAM) device which may be operated in synchronization with an external clock signal input from the outside has been used. The initial form of the SDRAM device is a Single Data Rate (SDR) SDRAM device which input and output data in synchronization with a rising edge of an external clock signal to input/output data through a data pin.
To further increase the operation speed, a Double Data Rate (DDR) SDRAM device which processes two data in one clock cycle is being used. Here, the DDR SDRAM device is synchronized with both a rising edge and a falling edge of an external clock signal input from the outside to input/output two data consecutively. Therefore, although the frequency of the external clock signal is not increased, the DDR SDRAM device may realize at least twice the bandwidth of the conventional SDR SDRAM device and thus the DDR SDRAM device may operate at a high speed.
Examples of the DDR SDRAM device are a DDR2 SDRAM device, a DDR3 SDRAM device, and a DDR4 SDRAM device. A DDR
SDRAM device performs a 2-bit prefetch operation during an input/output to support a burst length (BL) of two bit data, and a DDR2 SDRAM device performs a 4-bit prefetch operation during an input/output to support a burst length (EL) of four bit data. A DDR3 SDRAM device performs an 8-bit prefetch operation during an input/output to support a burst length (BL) of 8 bit data, and a DDR4 SDRAM device supports a burst length (EL) of 8 or 10 bit data. Here, the burst length of 10 bit data signifies that 10 bit data are consecutively input/output through a data pin in synchronization with a clock edge of an external clock signal. Hereafter, a scheme where a plurality of data is being input/output consecutively is referred to a burst transfer scheme.
FIGS. 1A and 1B are timing diagrams illustrating a burst transfer scheme supported in a conventional DDR4 SDRAM device. FIG. 1A shows a timing diagram of a burst transfer scheme in an 8-bit burst length (BL8) transfer mode, and FIG. 1B shows a timing diagram of a burst transfer scheme in a 10-bit burst length (BL10) transfer mode.
Here, in describing the conventional technology of FIGS. 1A and 1B, a burst transfer scheme of a read operation is taken as an example, where an internal clock signal IN_CLK obtained by dividing the frequency of an external clock signal EX_CLK by 2 is used. Here, the frequency-divided internal clock signal IN_CLK is used to sufficiently secure the margins of read commands RD_CMD<1> and RD_CMD<2>.
Referring to FIG. 1A, in the 8-bit burst length (BL8) transfer mode, the clock gap (tCCD, which is CAS command to CAS Command delay) between the read commands RD_CMD<1> and RD_CMD<2> is set to 4 tCK, where tCK denotes one cycle of the external clock signal EX_CLK. Therefore, when the read commands RD_CMD<1> and RD_CMD<2> are input in synchronization with a rising edge of an internal clock signal IN_CLK, 8 bit read data G1 and G2 are sequentially output through a data pin after a read latency RL1, where the read latency RL1 is determined based on the time that a corresponding read command RD_CMD<1> or RD_CMD<2> is applied. Here, the read latency RL1 is defined as a sum of a CAS latency CL1 and an additive latency AL1.
Referring to FIG. 1B, in the 10-bit burst length (BL10) transfer mode, the clock gap tCCD between the read commands RD_CMD<1> and RD_CMD<2> is set to 6 tCK, where tCK denotes one cycle of the external clock signal EX_CLK. Therefore, when the read commands RD_CMD<1> and RD_CMD<2> are input in synchronization with a rising edge of an internal clock signal IN_CLK, 10 bit read data G3 and G4 are consecutively output through a data pin after a read latency RL2, where the read latency RL2 is determined based on the time that a corresponding read command RD_CMD<1> or RD_CMD<2> is applied.
The burst transfer scheme supported by the conventional DDR4 SDRAM device has the following features.
Referring to FIG. 1A, in the 8-bit burst length (BL8) transfer mode, the read data G1 and G2 may be sequentially output without a gap between the read data G1 and G2 that are consecutively output based on the consecutive read commands RDCMD<1> and RD_CMD<2>. In the 10-bit burst length (BL10) transfer mode, however, which is illustrated in FIG. 1B, there is a gap equal to 1 tCK between the read data G3 and G4 that are output corresponding to the consecutive read commands RD_CMD<1> and RD_CMD<2>, respectively. Due to such a gap in the 10-bit burst length (BL10) transfer mode, a decrease in the data transfer rate per unit time (which is bandwidth) may occur. If the clock gap tCCD between the read commands RD CMD<1> and RD_CMD<2> is set not to 6 tCK but to 5 tCK, the decrease in the data transfer rate per unit time may be prevented. However, the cycle of the internal clock signal IN_CLK does not work with the clock gap tCCD being equal to 5 tCK, the clock gap tCCD between the read commands RD_CMD<1> and RD_CMD<2> is not set to 5 tCK. This is because a portion A of the internal clock signal IN_CLK corresponding to 5 tCK of the external clock signal EX_CLK is not a rising edge just as in the external clock signal EX_CLK but a falling edge.
As described above, since the internal clock signal IN_CLK has a twice as wide clock cycle as the external clock signal EX_CLK, the internal clock signal IN_CLK may satisfy the clock gap tCCD between the read commands RD_CMD<1> and RD_CMD<2> corresponding to the even-number cycles of the external clock signal EX_CLK, such as 2 tCK, 4 tCK, 6 tCK and the like. Therefore, in case of the 10-bit burst length (BL10) transfer mode, since the clock gap tCCD between the read commands RD_CMD<1> and RD_CMD<2> is set to 6 tCK, a clock gap of 1 tCK occurs between the read data G3 and G4 that are consecutively output and thus the data transfer rate per unit time (which corresponds to bandwidth for data transfer) decreases.